1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a trench isolation structure.
2. Description of the Prior Art
In recent years, accompanying the progress in technology to attain higher integration of the semiconductor device, there have been growing demands not only for the miniaturization of the device structure but also for the miniaturization of the isolation structure. For this purpose, in place of the conventional LOCOS (Local Oxidation of Silicon) method, the Trench Isolation method, suited well for the formation of minute structures of element isolation, has been proposed.
The formation of an isolation structure by the Trench Isolation method is carried out in the following way. First, by etching the semiconductor substrate deep enough to separate two neighbouring device elements, a sunken section or a trench is formed. Next, after an insulating film such as a silicon oxide film is formed so as to fill up this trench, the treatment for planarization is made by the chemical mechanical polishing (CMP) or such to remove the insulating film lying a region other than that within the trench, whereby an isolation region which is composed of the insulating film (the buried insulating film) buried in the trench is formed.
In a conventional method of manufacturing a semiconductor memory device such as a SRAM (Static Random Access Memory), a transistor is formed on a semiconductor substrate where such a trench isolation structure as described above is formed, in the following way.
FIG. 11 to FIG. 13 are a series of cross-sectional views illustrating the steps of a manufacturing method of a MOS (Metal Oxide Semiconductor) transistor having a LDD (Lightly Doped Drain) structure.
First, on a silicon substrate 101 where an isolation region 102 with a trench isolation structure is formed, a thermal oxidation film (not shown in the drawings) which is to serve as a gate insulator is formed, and thereafter a doped polycrystalline silicon film is formed. By patterning this polycrystalline silicon film by lithography and etching, a gate electrode 104 is then formed (FIG. 11(a)).
Next, using the gate electrode 104 as a mask, the ion implantation is performed to form LDD regions 105, where the concentration of implanted dopant is low, and the conductive type is opposite to the one of the substrate (FIG. 11(b)).
Following that, a silicon oxide film 106 is formed to cover the gate electrode 104 (FIG. 11(c)), and then by anisotropic etching of this film 106, sidewalls 106a are formed on lateral faces of the gate electrode 104 (FIG. 12(a)). This anisotropic etching (referred to as “sidewall etch back” hereinafter) is necessary to remove silicon oxide thoroughly on both the gate electrode 104 and the silicon substrate 101, so that the overetching is needed to be performed in the removal. However, this overetching also causes the etching of the buried insulating film of the silicon oxide film inside the trench isolation region 102, which leads to a lowering of the top surface of the buried insulating film with respect to the substrate surface plane.
Next, a channeling stop film 107 is formed on the surface, as shown in FIG. 12(b). The channeling stop film 107 is silicon oxide film, which is used to prevent channeling of a dopant in the subsequent step of an ion implantation to form source/drain regions 108. The source/drain regions 108 are formed by the ion implantation with a high dose through the channeling stop film 107. The sidewalls 106a are used as mask to form LDD regions 105a beneath the sidewalls 106a. In these way, a LDD structure is formed, wherein the region of the low dopant concentration of LDD region is located in neighbor with the region of the high dopant concentration of source/drain region.
Subsequently, an etching stopper film 109 of a silicon nitride film is formed, following an interlayer insulating film 110 of a silicon oxide film or such is formed (FIG. 12(c)).
A contact hole 111 is then formed on the source/drain region 108 by the lithography and etching (FIG. 13(a)). After that, using the sputtering method, a barrier metal film is formed inside the contact hole, and subsequently, using the CVD (Chemical Vapour Deposition) method, the contact hole is filled up with a metal film of W or such, whereby a contact is formed (not shown in the drawing).
Recently, in order to meet the requirements of the miniaturization and higher integration, the contact holes tend to be opened in the vicinity of trench isolation region. It can happen that the contact holes are formed overlapping to the isolation region, due to the alignment shift or the like. Beside, source/drain regions tend to have a shallower junction depth for the shrinkage of the transistor size. Thus, a problem of generating the leakage between the contact and the substrate may arise, as shown in FIG. 13(b).
This problem is caused by a lowering of the top surface of the buried insulating film in the trench isolation region 102, with respect to the substrate surface plane, as shown in FIG. 12(a), which originate from the overetching in the step of the sidewall etch back. In general, the overetching is carried out with additional 50% thickness of the whole thickness of the film subjected to etching. In other word, the thicker the film subjected to etching is, the longer etching period becomes. Since the silicon oxide film 106 for the formation of sidewalls has a considerable thickness of more than 100 nm or so, sidewall etch back must be performed for a long time. Therefore, the top surface of the buried insulating film in the isolation region becomes lowered to a deeper level. Moreover, if silicide films are formed on the source/drain regions, the top surface of the buried insulating film is lowered further to a still deeper level because of a treatment of removing the oxide film lying on the substrate.
When the contact holes 111 are formed overlapping to the isolation region 102 with the top surface level dropped, the bottom of the contact holes reaches to a still deeper level than the level of the junction depth of the source/drain regions 108 after the removal of the etching stopper film 109 on the top of the surface of the isolation region 102. At the section 112 which is dug into deeper than the junction depth of the source/drain region in the step of the removal of the etching stopper film 109, a leakage between the contact and the substrate occurs. This leakage becomes more likely to take place when the junction depth of the source/drain regions is set to be formed shallower.
Furthermore, crystal defects become more apt to be formed on the substrate surface by the overetching for the longer time period in the step of the sidewall etch back, which result in the deterioration of device characteristics such as the generation of a leakage.